In recent years, remarkable evolution has made on the thinning of the semiconductor chip and the downsizing of the chip. In particular, the thinning is required in the IC cards with built-in semiconductor IC chips, such as a memory card and a smart card. Further, the downsizing of the chip is required in LED or LCD driving devices and the like. With the increase in these demands from now, the needs for the thinning of the semiconductor chip and the downsizing of the chip are thought of as being increased much more.
These semiconductor chips are obtained, by thinning a semiconductor wafer to a predetermined thickness in the backgrinding step, an etching step or the like, and then dividing the semiconductor wafer into individual chips through a dicing step. In this dicing step, a blade dicing method of cutting the semiconductor wafer with a dicing blade has been used. In this blade dicing method, the cutting resistance by the blade is put directly on the semiconductor wafer at the time of cutting, so that a microscopic crack (or chipping) sometimes occurs in the semiconductor chip by this cutting resistance. Occurrence of the chipping does not only deteriorate outer appearance of the semiconductor chip, but also in some cases, there is a risk that even a circuit pattern on the chip is damaged, for example, a damage of chips is occurred due to lack (or insufficiency) of the transverse strength (or deflective strength) at the time of picking up. Further, in the foregoing physical dicing step using such a blade, it is impossible to set the width of a kerf (also referred to as a scribe line or a street) which is an interval between chips to less than the thick blade width. As a result, the number (yield) of chips gotten from a sheet of wafer decreases. Further, a long time period to be taken for the processing of the wafer is also a problem.
In the dicing step, use is also made of any of various kinds of methods, other than the blade dicing method. There is a DBG (i.e. dicing before grinding) method of, in view of the difficulty in carrying out the dicing after the thinning of the wafer, forming in first a groove with a predetermined thickness in the wafer, and then carrying out a grinding step, and thereby for achieving both the thinning and the singulation into chips at the same time. This method has the advantage that although the kerf width is similar to that in the blade dicing method, the transverse strength of the chip is increased, so that a damage of the chip can be suppressed.
Further, there is a laser dicing method of carrying out a dicing step with a laser. The laser dicing method has the advantage that a kerf width can be narrowed and the laser dicing method is a dry process. However, there is a disadvantage that a wafer surface is contaminated with a sublimate at the time of cutting with a laser. For this reason, the wafer surface sometimes necessities being subjected to a pretreatment of protecting it with a predetermined liquid protecting material. Further, the foregoing dry process has not yet led to achievement of a complete dry process. Further, the laser dicing method allows a further speeding-up of the processing rate, compared to the blade dicing method. However, the laser dicing method remains unchanged in carrying out a processing along every one line, and therefore it takes a certain time period for producing an extremely small chip.
In a case of using a wet process, such as a water-jet method of carrying out a dicing step with a water pressure, there is a possibility that a problem occurs in the material which is sensitive to a surface contamination, such as an MEMS device, a CMOS sensor, and the like. There is also a disadvantage that a kerf width cannot be narrowed only to some extent, so that a chip yield is low.
The stealth dicing method of forming a modifying layer with a laser in the thickness direction of the wafer, and then splitting the modifying layer by expansion to singulate the wafer, has the advantage that a kerf width can be reduced to zero and a processing can be carried out in a dry state. However, a transverse strength of the chip tends to be decreased by the thermal history at the time of forming the modifying layer. Further, silicon debris sometimes occurs at the time of splitting the modifying layer by expansion. Further, there is a risk that the collision of each adjacent chips may be bring about short (or insufficiency) of the transverse strength.
Further, as a combined method of the stealth dicing and the dicing before grinding, there is a chip-singulation method corresponding to a narrow scribe width, which forms in first a modifying layer with only a predetermined width prior to the thinning, and then carrying out a grinding step from the backing-face side, thereby for achieving the thinning and the singulation into chips at the same time. This technique improves the disadvantages of the above mentioned process, and has the advantage that a kerf width is zero and a chip yield is high and also a transverse strength is increased, because a silicon modifying layer is cleaved and singulated by a stress in the wafer backgrinding step. However, because singulation is performed in the backgrinding step, a phenomenon is sometimes occurred, in which an end side of the chip collides with an adjacent chip, and thereby that the chip corner is chipped.
Further, a dicing technology by a plasma dicing method has been proposed (for example, see Patent Literature 1). The plasma dicing method is a method of dividing a semiconductor wafer, by selectively etching a portion which is not covered with a mask, using plasma. If this dicing method is used, segmentation of chips can be achieved selectively, and even if the scribe line is curved, the segmentation is possible with no trouble. Further, as the etching rate is very high, in recent years, this dicing method is considered one of the most suitable steps for the segmentation into chips.